Serial digital data communication is broadly divided into two classes of operation: synchronous and asynchronous. Synchronous digital data communication refers to the transfer of system clocked digital data. It occurs when the digital data being transferred must conform to specific system timing constraints and boundaries, which partition the digital data into referenced intervals of time. Any transition of the digital data must occur at these boundaries. Asynchronous digital data communication refers to the transfer of digital data which does not adhere to the specific system timing constraints and boundaries and may be clocked or unclocked digital data.
Synchronous digital data is used most commonly in communication systems and information and data processing systems. Communication systems usually employ a method for synchronizing to a known information exchange rate. Information and data processing systems utilize synchronous digital data to control the flow of information, data, and events which ensures an orderly execution of various operations and logical decisions. Synchronous systems used in serial digital data communications produce a stream of data at a fixed clock rate, where the clock controls not only the data timing within a character, but also the character-to-character timing as well.
Asynchronous digital data is commonly used in control systems where the orderly execution of operations is controlled by a number of completion and initiation signals, often termed "handshaking". The completion signal of one set of operations will initiate the next consecutive set of operations. Asynchronous protocols used in serial digital data communications treat each character as a different message, and the characters appear in the data stream at arbitrary relative times. Within each character however, the data information (bits) is transmitted at a fixed predetermined clock rate. The protocols are actually synchronous within a character and asynchronous between characters, but they are called asynchronous, since the timing between characters is their distinguishing characteristic.
Conversion of asynchronous digital data to and from synchronous digital data is frequently performed when the synchronous intracharacter bit rate of the asynchronous digital data matches the synchronous digital data rate within tolerable limits. However, when the difference between the intracharacter bit rate of the asynchronous digital data and the synchronous digital data rate exceed tolerable limits, specialized circuits and data formats or protocols must be incorporated, such as the Asynchronous-to-Synchronous Data Concentration System presented in U.S. Pat. No. 4,048,440.
As described here and below, the present invention provides enhancements to the Asynchronous-to-Synchronous Data Concentration System presented in U.S. Pat. No. 4,048,440, exemplified by the increased tolerance to bit rate mismatch and programmable character length selection. Also, the invention can be implemented using total digital design architecture enabling gate array integrated circuit implementation.